Decoding Energy Estimation of an HEVC Hardware Decoder

Published: 01 Jan 2018, Last Modified: 14 Nov 2024ISCAS 2018EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: This paper investigates the energy a hardware decoder needs for decoding and displaying an HEVC-coded bit stream. Therefore, energy measurements are performed on a high amount of different bit streams. The results are used to validate the estimation accuracy of various decoder energy models. Furthermore, from power measurements, two new models are derived and proposed. The results show that all models are capable of estimating the decoding energy with a mean estimation error below 5%, where the lowest error of 1.04% was found for one of the proposed models. Furthermore, trained parameter values are given quantifying the influence of various sequence properties on the decoding energy: the resolution, the frame rate, the playback time, and the file size of the bit stream.
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