NeRF-Navi: An Energy-Efficient NeRF 3-D Path Planning Processor With Reconfigurable Approximate/Accurate Bit Offloading Core

Seryeong Kim, Seokchan Song, Wonhoon Park, Junha Ryu, Gwangtae Park, Sangyeob Kim, Soyeon Kim, Donghyeon Han, Hoi-Jun Yoo

Abstract: An implicit neural representation (INR) continuously encodes a 3-D space using a neural network. Neural radiance field (NeRF), a type of INR, achieves a high path planning success rate of 98.6%. It leverages the continuous space representation ability of NeRF. However, accelerating NeRF path planning on edge devices faces limitations due to the excessive computational load. In this article, we present NeRF-Navi, an accurate and energy-efficient 3-D NeRF path planning processor with three key features: 1) dual-attention neural path sampling (DANPS) engine uses map and collision attention to reduce the number of redundant batches, which saves 96.2% of system energy; 2) approximate-accurate (A2) core with an error-compensable reduction tree (ECRT) introduces three approximate computing modes with less than 1.6% accuracy overhead; bit sparsity boosting logic (BSBL) increases bit sparsity and reduces the compensation overhead of ECRT; and the A2 core and BSBL achieve a 26.2% reduction in total system energy; and 3) outlier channel bit-offloading core and bit allocator (BA) that offload sparse MSB bits of outlier channels, reducing total system energy by 36%. NeRF-Navi is fabricated in a 28-nm logic CMOS process and occupies a 6.48-mm2 die area. NeRF-Navi finally achieves 1.2– $8.8{\times }$ lower path planning energy per task and 1.7– $124{\times }$ lower EDP than the previous 3-D path planning processor.

External IDs:dblp:journals/jssc/KimSPRPKKHY25