SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation

Hyeyeong Lee, Joonhyung Kim, Jongsun Park

Abstract: Since power consumption reduction has been of particular interest, lowering supply voltage has been widely adopted in system on a chip (SoC) design. In static random access memory (SRAM), read operation with low supply voltage suffers from large read delay to develop the bit-line (BL) voltages using reduced bitcell current. In addition, since process-voltage - temperature (PVT) variations in bitcell current deteriorates at low supply voltage, deciding sense amplifiers (SA) activation time is another issue to consider. In this paper, to address the uncertainties of SA activation timing, we propose the bit-line (BL) boosting circuit that supports timing-aware BL sensing. The proposed BL boosting circuit also speed up the BL develop time. The BL boosting circuits have been implemented using 28nm CMOS process, and with 1000 Monte-Carlo simulation, the mean and standard deviation of read delay are reduced by 53.0% and 50.2%, respectively.