Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models

Daniel Mueller-Gritschneder, Marc Greim, Ulf Schlichtmann

Abstract: This article gives an overview of fault injection into embedded processors at VP level. The ETISS processor simulator is integrated into a SystemC/TLM VP and extended by plugins. A plugin for switching to RTL-level simulation for accurate simulation of soft errors is described. Experimental results for a control system and the OpenRISC processor are given.