Every test makes a difference: Compressing analog tests to decrease production costs

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Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan

Published: 01 Jan 2016, Last Modified: 15 Oct 2025ASP-DAC 2016EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: We introduce a methodology for automated test compression during electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find optimal solutions for these computationally hard integrals. We demonstrate with an op-amp, VCO and CMOS inverter that the method consistently reduces the length of each test by an average of 93%.