Spatially Efficient In-Memory Addition Through Destructive and Non-Destructive Operations

Alvaro Velasquez, Benjamin Shaia

Abstract: Compact in-memory circuits for implementing n-bit addition with varying degrees of destructive operations are presented. The non-destructive, semi-destructive, and fully-destructive adder variants are posed as bounded model checking procedures for design synthesis. The resulting designs are shown to be state-of-the-art in the number of execution steps required for computation when compared to other serial adders.