Power-gating-aware scheduling with effective hardware resources optimization

Nan Wang, Wei Zhong, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu

Abstract: Highlights•Both the leakage power and area of data-path are optimized during scheduling.•Both register usage and interconnection cost are well evaluated during scheduling.•The number of retention registers is minimized to reduce the leakage power.•The order of scheduling operations is optimized to improve the scheduling result.