Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array

Jinseok Kim, Jongeun Koo, Taesu Kim, Yulhwa Kim, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim

Abstract: We introduce a SRAM-based binary neural network (BNN) hardware which uses a single 6T SRAM cell for XNOR operation for the first time. The cell is 45% smaller than the previous 8T bitcell for XNOR operation. We also propose an in-memory calibration and batch normalization to achieve more reliable operation under the presence of process variation.