FlexSiMArch: An Extensible Simulator for Research and Development in Secure-by-Design Processor Technologies

Sameer Mankotia, Daniel Leon

Abstract: Successful attacks on digital systems have been prevalent for decades. Several incremental solutions have been implemented including: Non-executable Stack, Control Flow, Pointer/Buffer Bounds, Trusted Execution, Stack Canaries, and Address Space Layout Randomization. However, preventing lowlevel attacks on digital systems is still an unsolved major challenge. Four out of the top ten KEV (Known Exploited Vulnerabilities) fall within the category of low-level weakness. We believe a top-to-bottom solution that includes co-designed and/or well-integrated: languages for requirements, design, and code, development processes, hardware, and tool-sets for the development of secure-by-design digital systems is much needed. We also believe that such a solution must be incrementally implemented and adequately integrated with current design and development processes and tools to be successfully adopted. Toward this goal, we introduce FlexSiMArch, an easily extensible Python-based simulator that supports the rapid development and evaluation of new digital processor architectures and instruction sets. Currently, FlexSiMArch supports RISC-V (RV32I, RV64I). We are using FlexSiMArch to simulate and evaluate a novel hardware-based and instruction-level security policy enforcement technology (BHPol).