NeuronFlow: A Hybrid Neuromorphic - Dataflow Processor Architecture for AI Workloads

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Orlando Moreira, Amirreza Yousefzadeh, Fabian Chersi, Ajay Kapoor, Rik-Jan Zwartenkot, Peng Qiao, Gokturk Cinserin, Mina A. Khoei, Menno Lindwer, Jonathan Tapson

Published: 2020, Last Modified: 02 May 2026AICAS 2020EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: We present a novel computing architecture which combines the event-based and compute-in-network principles of neuromorphic computing with a traditional dataflow architecture. The result is a fine-grained dynamic dataflow system which avoids the coding issues intrinsic to spiking systems, and is suitable for both procedural workload and deep neural network (DNN) inference. The architecture is particularly suitable for computation of sparse CNNs and low-latency applications. We present results from GrAIOne, the first chip designed using the NeuronFlow architecture, which has 200 704 neurons implemented in a 28nm HPC + process.