High-Speed Post-Quantum Cryptoprocessor Based on RISC-V Architecture for IoT

Shahriar Hadayeghparast, Siavash Bayat Sarmadi, Shahriar Ebrahimi

Abstract: Public-key plays a significant role in today’s communication over the network. However, current state-of-the-art public-key encryption (PKE) schemes are too complex to be efficiently employed in resource-constrained devices. Moreover, they are vulnerable to quantum attacks and soon will not have the required security. In the last decade, lattice-based cryptography has been a progenitor platform of the post-quantum cryptography (PQC) due to its lower complexity, which makes it more suitable for Internet of Things applications. In this article, we propose an efficient implementation of the binary learning with errors over ring (Ring-BinLWE) on the reduced instruction set computer-five (RISC-V) platform. Our field-programmable gate array (FPGA) implementations improve the speed of scheme operations by more than 51% in terms of CPU cycles compared to previous work. The proposed hardware module has low complexity and only imposes around 6%–9% overhead to the original core. Moreover, it has constant-time operations and is resistant to timing attacks. Besides, a more reliable fault-resilient variant of the architecture with 1% area overhead is proposed. According to the application-specific integrated circuits (ASICs) implementations, the proposed architecture achieves at least 32%, 79%, and 50% lower power, energy, and area consumption compared to the previous work, respectively.