Hierarchical Behavioral Learning-Based Dynamic Electromigration Analysis for Signal Networks

Yupeng Hu, Yapeng Li, Jindong Tu, Tinghuan Chen, Qi Sun, Cheng Zhuo

Abstract: In this work, we propose a novel post-layout netlist simplification, modeling, and agile electromigration (EM) analysis framework. First, we implement a hierarchical parasitic extraction strategy to partition the top-level post-layout netlist into functional modules, followed by a worst-case circuit analysis to quickly identify wires with potential for EM violations within each module. Next, the feedforward neural networks (FFNs) and long short-term memory (LSTM) models are employed to construct circuit behavioral models encompassing the input-output behavior and current responses of specified internal nodes. These models are subsequently converted into Verilog-A format for transistor-level simulation. Finally, we substitute the modules with generated Verilog-A models to reduce the circuit complexity. Our framework can significantly accelerate the simulation and EM analysis under different excitation signals. The experiments show that our framework yields up to $38.02\times $ speedup in simulation time required for transistor-level EM analysis over the commercial tool, together with excellent accuracy.

External IDs:dblp:journals/tcad/HuLTCSZ25