11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné

Abstract: Augmented reality (AR) products require energy-efficient systems-on-chip (SoCs) for machine learning (ML), neural networks (NNs), and image signal processing (ISP) applications [1]. These SoCs must be high-performance, yet low power with compact form factors. They are heavily constrained by the area footprint, while the third dimension is usually left with ample space. Moreover, frequent access to off-chip memories can be prohibitively expensive in terms of latency and energy for AR devices. Fortunately, recent advances in 3D integration allow integration of additional logic and memory into the SoC without area footprint cost. In particular, face-to-face (F2F) stacking with hybrid bonding (HB) allows for high bandwidth (BW) connections between dies without incurring substantial energy overhead. We demonstrate, for the first time in the AR domain, a 3D integrated SoC using face-to-face hybrid-bonding technology to show: (1) deployment of larger workloads not previously feasible on an iso-form factor baseline due to memory capacity limitations and strict execution time and energy requirements, and (2) system-level energy and execution time savings (up to 40% for each) for our prototype AR SoC within tight form factor constraints.