An Efficient Paillier Homomorphic Encryption Circuit With Optional CRT Acceleration for IoT

Jundong Feng, Xiaoliang Zhang, Zeljko Zilic, Qinfen Hao, Junchao Wang

Abstract: The Paillier scheme, widely recognized as the most prevalent additive homomorphic encryption paradigm, faces significant challenges in Internet of Things (IoT) applications due to latency, power, and hardware overhead. This article proposes an efficient Paillier homomorphic encryption circuit for IoT, integrating Chinese remainder theorem (CRT) acceleration. First, we propose an algorithm framework tailored for hardware reuse that supports multiple functionalities of the Paillier scheme. It introduces an montgomery modular multiplication (MMM) algorithm with superior area-time product (ATP) to implement core computations, and reduces hardware cost by reusing MMM to replace other computational units. Then, a computational unit reuse architecture based on the algorithmic framework is designed to reduce resource overhead. Moreover, a split-coupled MMM circuit design is proposed to counteract computational resource expansion induced by CRT operations. The hardware design is synthesized under SMIC 40 nm CMOS technology. The evaluation shows that the proposed scheme provides a high-performance Paillier circuit design with less area and lower power, offering an effective solution for data security processing in IoT.

External IDs:dblp:journals/iotj/FengZZHW25