A 12 bit 250 MS/s SAR ADC using level shifted pseudo bottom plates sampling for high conversion rate and wide input amplitude

Chao Zhao, Hao Zhang, Jie Shao, Can Shi, Dongyang Han, Chengyu Pan, Xusheng Tang

Abstract: This paper describes a 12 bit 250 Ms/s time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A novel level shifted pseudo bottom plates sampling (LSPBS) method is proposed. In contrast to conventional top plates sampling methods, LSPBS effectively mitigates clock feedthrough and charge injection while sustaining a high sampling rate, thereby enhancing the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) of the ADC. And LSPBS can realize level shift of signals with wide input range, breaking the trade-off between transistor breakdown voltage and signal input range. A metastable elimination comparator is proposed to avoid the problem of ADC circuit failure due to metastable state. In addition, a wide-range DC-coupled buffer is proposed to improve the input range of the SAR ADC and enhance the SNR and linearity. The proposed SAR ADC was implemented using a 28-nm CMOS technology. The capacitance calibration is performed through DEM, without any digital calibration involved. At Nyquist input frequency and a 250 MS/s sampling rate, a SNDR of 59.27 dB and a SFDR of 74.61 dB are achieved, respectively. The core occupies 780μm × 222μm, and consumes a total power of 4.89 mW.