Variation Aware Performance Analysis of TFETs for Low-Voltage Computing

Vikash Sehwag, Saurav Maji, Mrigank Sharad

Abstract: Tunnel field-effect transistors (TFETs) can outperform MOSFETs in low power electronics due its low leakage current and excellent threshold swing. In recent years, the application of TFETs in the design of sub-threshold cores have been proposed, operating at few hundred millivolts. However process induced variations need to be considered while assessing the achievable benefits of TFETs at such low voltages. Also, the non-idealities associated with distribution and regulation of such low supply voltages needs to be modeled. Here we present the analysis of process variations effect on device performance metrics (Energy consumption, Operating frequency) of digital design comprising AlGaSb/InAs Heterojunction TFETs (HTFET), InAs/Si HTFETs and MOFETs. Our evaluation based on calibrated TFET compact models show that TFET circuits are less affected than the MOSFET counterparts from process variation. The energy-delay product of TFET and CMOS is compared, considering process variations and supply voltage noise. Further, a feasibility study of low voltage, low ripple supply distribution for sub-threshold TFET blocks based on distributed Digital Low Drop Out (LDO) is presented.