Design of Reversible Shift Registers Minimizing Number of Gates, Constant Inputs and Garbage Outputs

Partho Ghose, Md. Naimur Rahman, Md. Masbaul Alam Polash, Uzzal Kumar Acharjee

Abstract: Reversible logic is an emerging technology that plays an important role in the fields of low power computation and can be applied in cryptography, communications, quantum computing etc. Reversible shift registers are one of the most important elements in fabricating reversible memory circuits. In this paper, we present efficient design of different reversible shift registers such as Serial In Serial Out, Serial In Parallel Out, Parallel In Serial Out and Parallel In Parallel Out registers. We have also outlined appropriate lemmas to illustrate different properties of the proposed designs. Suitable algorithms for designing the reversible shift registers are also mentioned. Comparative analysis reveals that our proposed design requires minimal number of reversible gates and constant inputs, and also produces less number of garbage outputs than the state-of-the-art design. Furthermore, to clarify the validity of our design, all the proposed circuits have been simulated using DSCH3.

External IDs:dblp:conf/icacci/GhoseRPA18