Generalizable and Relation Sensitive Netlist Representation for Analog Circuit Design

Surya Penmetsa, Fahad Rahman Amik, Zhanguang Zhang, Yingying Fu, Yingxue Zhang, Wulong Liu, Jianye Hao

Abstract: The problem of transistor sizing is challenging due to the large design space and complex performance trade-offs. Conventional black-box optimization methods, such as Bayesian optimization, cannot leverage past experience. In this paper, we propose a novel state representation for analog circuits to capture the heterogeneity of connections between different components. Component types are encoded through an embedding lookup table, which enables learning transferable knowledge across circuits. Experiments on various designs demonstrate that the agent with transfer learning can reduce runtime significantly in both fine-tuning and zero-shot transfer settings compared to current SOTA baselines. Notably, when learning from scratch, our agent achieves at least 21% higher Figures of Merit (FoM) compared to the SOTA method.