PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing

Sharbani Purkayastha, Shyamapada Mukherjee

Abstract: In this paper, a new wirelength-driven placement model for UltraScale heterogeneous FPGAs have been developed and presented. The proposed algorithm applies a novel approach of utilizing the architectural information of the UltraScale heterogeneous FPGA to guide the placement from the initial stage of the proposed technique. The initial placement is followed by a cluster selection and net selection processes. The novelty of the proposed placement method lies in the fixed block-based cluster formation, segregation table and cell mapping to different placement sites. The segregation table and cell mapping methods are proposed to achieve a good global placement solution by consider a rough legalization and area congestion estimation. A new legalization procedure has been introduced to reduce legalization cost by employing delayed packing and cell mapping to BELs. A detailed placement phase is explored to refine the placement to achieve congestion free legal placement of cells with minimized wirelength. Experimental results have shown that the proposed algorithm achieves better results than the state-of-the-art FPGAs placement algorithms in terms of wirelength without using any expensive optimization framework.