Area-optimized montgomery multiplication on IGLOO 2 FPGAs

Pedro Maat C. Massolino, Lejla Batina, Ricardo Chaves, Nele Mentens

Abstract: This paper presents the first area-optimized Montgomery modular multiplication module on low-power reconfigurable IGLOO® 2 FPGAs, from Microsemi. In order to obtain a good response time with few resources, the FPGA pipelined Math blocks and the embedded memory blocks are fully leveraged. As a result, 256-bit modular multiplications can be done in 2.33 μs, at a cost of 505 LUT4 cells, 257 Flip Flops, 1 Math block and 1 64×18 RAM block. If more area resources are considered, a modular multiplication can be performed in 1.25 μ8 at a cost of 680 LUT4s, 341 Flip Flops, 2 Math blocks and 2 64×18 RAM blocks. This work is the first fundamental step towards area-efficient public-key cryptography on the Microsemi IGLOO® 2 FPGAs.