A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection

Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya

Abstract: A compact complementary metal-oxide semiconductor (CMOS) circuit for depressing synapses is designed for demonstrating applications of spiking neural networks for contrast-invariant pattern classification and synchrony detection. Although the unit circuit consists of only five minimum-sized transistors, they emulate fundamental properties of depressing synapses. The results of the operations are evaluated by both experiments and simulation program with integrated circuit emphasis (SPICE).