An Efficient Spiking Convolutional Architecture with Compressed Address Event Representation and Adaptive Delay Asynchronous Clocks

Zhenhui Dai, Li Lun, Zilin Wang, Jiawei Wang, Kunyu Feng, Yuan Wang, Dunshan Yu, Xiaoxin Cui

Abstract: In this paper, an efficient brain-inspired spiking convolutional neural network processor architecture is presented. This architecture supports sparse spiking convolutions with an event driven and highly parallel pipeline. A compressed address event representation is applied to record spikes, which represents the neuron firing results of adjacent 4 channels with a single address, reducing the storage and transmission overheads of spikes. We propose an adaptive delay asynchronous pipeline to address the performance degradation of pipelines caused by multi-layer adder trees. A FPGA prototype has been implemented on the Xilinx Virtex development board. The processor prototype achieves an efficiency of $28.3 \mathrm{GSOP} / \mathrm{W}$ and $0.035 \mathrm{~nJ} / \mathrm{SOP}$ at equivalent clock frequency of 300 MHz to 400 MHz.