Thermal-Aware Test Frequency Optimization

Wei-Shen Wang, Zhe-Jia Liang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li

Abstract: Thermal issues during testing of Very Large Scale Integration (VLSI) chips have become more severe as design complexity increases. Test frequency optimization is needed because high test frequencies can cause thermal damage to circuits under test (CUT), while low test frequencies can result in long test time. In this paper, we propose three techniques to minimize the test time of ATPG scan tests without peak temperature violation. First, we propose a single test frequency optimization using machine learning predicted power maps. Second, we partition a test schedule into subschedules and perform multiple test frequency optimization for each subschedule to further reduce test time. Third, we show that we can partition a test schedule by our proposed Power Gap to obtain an even shorter test time. Our experimental results show that the total test time at our optimized multiple test frequencies is 45.91% shorter than the total test time at the original single test frequency.