Investigation of Low Temperature Noise and Current Fluctuation for Advanced Transistors: Characterization and Modeling

Ran Cheng

Abstract: Low temperature CMOS (LT-CMOS) circuits are also essential parts to realize large-scale quantum systems or high performance computing processors. In order to develop an effective and reliable LT-CMOS circuits, LT device characterization, analysis and modeling based on nanoscale transistors is necessary and has been extensive studied in recent years. Random telegraph noise (RTN) is an inevitable source of dynamic variation and it is reported to be more complicated due to the more obvious quantum effect at low temperatures. In this work, we reviewed our work on LT RTN and the current fluctuation for sub-20 nm n- and p-FETs with ultrathin channel. The following topics are studied: 1. The impact of temperature on the trapping/detrapping mechanisms for the advanced Si CMOS, 2. the temperature dependence and gate/drain biases dependence of the drain current variation, 3. the quantum trap model at LT, 4. the current fluctuation model for near threshold circuit design, and 5. the machine learning method for complicated LT noise analysis. The more severe and complicated device noise/current fluctuation at low temperature is an inevitable issue for the LT-CMOS IC design. The in-depth mechanism study and modeling will help to understand the trap behavior and optimize the noise issues in the low temperature circuit design.