Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping

Yilu Chen, Zhifeng Lin, Xiaojian Liang, Zhijie Cai, Xiqiong Bai, Jianli Chen

Abstract: The decomposition of multiplexers (MUXes) implies the representation of n-to-1 MUXes in terms of basic logic gates. This decomposition significantly impacts the performance of the subsequent optimization and matching in technology mapping. In this brief, we propose a network-architecture-aware multiplexer decomposition that decomposes an n-to-1 MUX into one of two significantly distinct architectures. Specially, a delay-evaluation-based guidance scheme estimates the total delay of the two architectures and then selects the optimal architecture for decomposing. Experimental results demonstrate that our algorithm outperforms Yosys and Design Compiler.