P4-Ace: Resource-Efficient Optimization and Verification for Programmable Switches

Zixi Cui, Saifeng Hou, Le Tian, Yu Wang, Xiaoyu Yi, Yongjie Wang, Peng Yi, Hongchang Chen

Abstract: As network applications are increasingly offloaded to the programmable switches, program testing problems come to the fore, which means to verifying whether target devices have adequate resources to support user programs. In this paper, we present P4-Ace, a resource optimization and verification system for high-speed chip. After analysing table dependencies in the input program, P4-Ace designs a two-layer framework to generate the optimal mapping solutions with respect to all the hardware constraints while minimizing resource usage. We also propose a novel feedback mechanism between the two layers to accelerate the solving process. The experiment results show that P4-Ace uses up to 30% fewer hardware resources with at least 10X shorter verification time than state-of-the-art.