A Compact Full Pipeline Architecture of SM3 Algorithm with High throughput and High Efficiency

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Tuo Li, Chao Cheng, Changhong Wang, Ruiting Wang, Xiaofeng Zou, Dunshan Yu

Published: 01 Jan 2025, Last Modified: 09 Nov 2025ISCAS 2025EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: This paper presents a compact full pipeline architecture of SM3 algorithm with high throughput and high efficiency, which is applied in high-performance security computing and large-scale data stream processing. The algorithm is reconstructed and a full pipeline computing architecture is proposed to achieve high throughput. In order to optimize the timing of algorithm, a compact architecture of compression function is further proposed, in which the critical path is reorganized and the adder delay of the path is optimized using CSA. Registers multiplexing is employed on the architecture of message word expansion for reducing area cost. Additionally, block RAM is employed to replace logic of polling and shifting, further optimizing the timing and reducing the LUT resources cost. The proposed architecture is implemented on a Xilinx Virtex-7 FPGA, and experimental results show that the designed SM3 achieves a peak frequency of 243 MHz, a high throughput of 124.42 Gbps, and a high efficiency of 15.22 Mbps/slice.