A 1920×1080 129fps 4.3pJ/pixel Stereo-Matching Processor for Pico Aerial Vehicles

Pingcheng Dong, Zhuoyu Chen, Ke Li, Lei Chen, Kwang-Ting Cheng, Fengwei An

Abstract: This paper presents an energy-efficient stereo matching processor that fully leverages disparity and RGB images to achieve high-speed and low-power depth prediction in 28nm CMOS process. A data compression-based guided image filter is proposed to compensate for the accuracy degradation caused by insufficient aggregation paths with slightly extra hardware resources. Two SRAM architectures tailored for the aggregation and multi-linebuffer in stereo matching achieve a compact chip area of only $1.26 \mathrm{~mm}^{2}$, which enables 30-129fps dense depth throughput on full HD resolution $(1920 \times 1080)$ with only $57-147 \mathrm{~mW}$ power dissipation. Besides, its normalized energy dissipation outperforms the state-of-the-art in $28 \mathrm{~nm}$ CMOS by $9.6 \times$ even with a larger on-chip SRAM footprint.