VerilogLAVD: LLM-Aided Pattern Generation for Verilog CWE Detection

ACL ARR 2026 January Submission6676 Authors

Keywords: RTL Security, Vulnerability Detection, Verilog, Code Property Graph, LLM, CWE

Abstract:

LLMs often fail in hardware vulnerability detection due to the intrinsic semantic concurrency of HDLs (Hardware Description Language), where vulnerabilities arise from the interaction of multiple concurrent execution statements rather than a single sequential execution path.
To address the problem, we propose VerilogLAVD, a LLM-Aided Vulnerability Detection framework by generating executable Traversal Detection Patterns (TDPs), i.e. the rules describing how to find the evidence of vulnerabilities in Verilog HDL. We first introduce a Unified Verilog Property Graph (VeriPG) that explicitly models parallel semantics by combining AST, CFG, and DDG. Furthermore, a semantic validation mechanism is designed to constrain and filter the LLM-generated TDPs. By executing these validated TDPs on VeriPG, our method produces stable and deterministic detection results. Experiments demonstrate that VerilogLAVD improves the F1 score by 133% compared to LLM-based methods. Furthermore, the framework successfully identifies real-world hardware vulnerabilities in open-source hardware design repositories.

Paper Type: Long

Research Area: Code Models

Research Area Keywords: vulnerability detection,formal methods with LLMs

Contribution Types: NLP engineering experiment

Languages Studied: Verilog

Submission Number: 6676