Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation

Sangjin Kim, Soyeon Um, Wooyoung Jo, Jingu Lee, Sangwoo Ha, Zhiyong Li, Hoi-Jun Yoo

Abstract: This paper presents Scaling-CIM, an energy-efficient eDRAM-IMC with the dynamic-scaling readout for SQNR boosting and ADC overhead reduction. Dynamic Scaling ADC boosts SQNR of multi-bit operation even with low-bit ADC. Adaptive analog bit-parallel accumulation reduces the redundant ADC operation. Also, layer-wise adaptive bit-truncation search further enhances efficiency on benchmarks. The accelerator is fabricated in 28nm CMOS technology and occupies $2.03\mathrm{m}\mathrm{m}^{2}$ die area. It achieves 39.7 TOPS/W energy efficiency on ResNet-18 benchmark and $ 6.8\times$ higher efficiency FoM compared to the previous IMC-based accelerator.