Throughput-Optimized Implementation of Isogeny-based Cryptography on Vectorized ARM SVE Processor

Pengchang Ren, Reiji Suda, Vorapong Suppakitpaisarn

Abstract: We present the first implementation of Supersingular Isogeny Key Encapsulation (SIKE) using ARM's Scalable Vector Extension (SVE), aiming to maximize throughput. Large integer multiplications in SIKE can be accelerated by using 64-bit integer multiplication instructions available in SVE, which was not available in previous work. The main problem is at addition with carry: SVE does not natively support add-with-carry or reduced radix. We propose to handle carries using predicate instructions. As a result, 3.4 times higher throughput was obtained on Wisteria/BDEC-01 (Odyssey) powered by Fujitsu A64FX CPU compared with SIDHv3.5, an ARMv8 assembly implementation of SIKE developed by Microsoft.