A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems

Xiaohua Huang, Han Liu, Woogeun Rhee, Zhihua Wang

Abstract: This paper describes a low-complexity digital-intensive in-band noise and out-of-band noise reduction method for ΔΣ fractional-N bang-bang digital PLLs (BB-DPLLs). The use of only a 4b digital-to-time converter (DTC) with auto-tuned delay cells provides a moderate way to mitigate the phase folding effect in the fractional-N BB-DPLL for decent in-band noise performance. An 8-tap hybrid finite-impulse response (FIR) filter is also utilized to suppress the out-of-band noise caused by the ΔΣ modulation in a wideband PLL. A prototype ΔΣ BB-DPLL is implemented in 65nm CMOS. Experimental results show that the proposed methods reduce the in-band phase noise by about 11dB and both the out-of-band noise and the fractional spurs by about l8dB with the maximum linearity requirements of 4b and 3b for the DTC and the FIR filter.