Graphene-based area efficient power planning architecture design methodology for nanomagnetic logic implementation

Santhosh Sivasubramani, Sanghamitra Debroy, Swati Ghosh Acharyya, Amit Acharyya

Abstract: In this study, we introduce the power planning architecture design for the implementation of Nanomagnetic Logic (NML) devices along with the proposed multi-phase local on-chip graphene integration and the clock design. To efficiently implement NML-based Integrated Chips augmenting CMOS toward rebooting computing, the major considerations are: on-board magnetic field (B-field) generation capacity, power planning, smart clustering, on-chip clock design, integration and its area occupancy. By performing Ansys Maxwell electromagnetic simulations, OOMMF micromagnetic simulations and theoretical modeling, we calculated the B-field generated by the sub-60 nm graphene wire and a group of such individual wires are further explored to propose the power planning architecture, design methodology. The proposed design along with the smart clustering enhances attenuation free data propagation as well as a reduction in the requirement of on-board resources to generate B-field for data propagation and computation in resource constrained applications. The proposed power planning architecture alongside multi-phase local on-chip graphene clock integration yields area efficient design for B-field generation to propagate data among nanomagnets for arithmetic computation.

External IDs:doi:10.1007/s11227-023-05449-z