Reinforcement Learning and Heuristics for Hardware-Efficient Constrained Code Design

ICLR 2025 Conference Submission13730 Authors

Keywords: reinforcement learning, bipartite matching, GNN, combinatorial optimization, feature engineering, hardware design optimization, logic synthesis

TL;DR: Reinforcement learning framework to optimize constrained code design, modeling codeword assignments as bipartite graph matching and using logic synthesis tools to minimize hardware complexity

Abstract: Constrained codes enhance reliability in high-speed communication systems and optimize bit efficiency when working with non-binary data representations (e.g., three-level ternary symbols). A key challenge in their design is minimizing the hardware complexity of the translation logic that encodes and decodes data. We introduce a reinforcement learning (RL)-based framework, augmented by a custom L1 similarity-based heuristic, to design hardware-efficient translation logic, navigating the vast solution space of codeword assignments. By modeling the task as a bipartite graph matching problem and using logic synthesis tools to evaluate hardware complexity, our RL approach outperforms human-derived solutions and generalizes to various code types. Finally, we analyze the learned policies to extract insights into high-performing strategies.

Primary Area: reinforcement learning

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Submission Number: 13730