An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing

Ahmad T. Sheikh, Aiman H. El-Maleh

Abstract: Highlights•A method based on logical implications and transistor sizing is proposed.•Implications are extracted between a set of selected source and target nodes.•The impact of adding a functionally redundant wire due to each implication is done.•To enhance circuit reliability to any level, STR based technique is then applied.•The proposed integrated method achieves similar reliability as STR with lower area.