On FPGA Security and Bitstream Reverse Engineering

Souhail Mssassi, Anas Abou El Kalam, Younes Jabrane

Abstract: This paper briefly surveys field-programmable gate arrays (FPGAs), focusing on the security features and reverse engineering schemes of SRAM-based FPGAs. We address security risks, including espionage and infrastructure attacks, which pose significant financial and operational challenges. This study contrasts the rigid nature of application-specific integrated circuits (ASICs) with that of reprogrammable FPGAs. Although FPGAs offer versatility and flexibility in various applications, their reliance on external nonvolatile memory to store netlist information introduces weaknesses. This is especially important in SRAM-based FPGAs, in addition to the efficient storage and transfer of bitstream files, because of the volatile nature of SRAM. This process is necessary to validate the integrity and honesty of the circuit information in the bitstream, particularly in the face of possible modifications or corruption introduced by attackers. We describe our approach to reverse engineering using tools such as Xilinx Design Language (XDL) and ISE design implementation.

External IDs:doi:10.1007/978-3-031-70411-6_2