Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS

Hyunmyung Oh, Hyungjun Kim, Daehyun Ahn, Jihoon Park, Yulhwa Kim, Inhwan Lee, Jae-Joon Kim

Abstract: We present an 8-transistor and 2-capacitor (8T2C) SRAM cell-based in-memory hardware for Binary Neural Network (BNN) computation. The proposed design accumulates multiplication results using a DRAM-like charge sharing operation, which makes it more tolerant to process variations and avoiding issues that hinder low voltage operations of conventional SRAM-CIM designs. Measurement results show that a $256 \times 64$ macro implemented in a 28 nm CMOS achieves 3182 TOPS/V at 0.7 V.