Autoformalizing Memory Device Specifications with Agents

Jan Ole Ernst, Dmitri Michelangelo Saberi, Thomas Zimmermann, Derek Christ, Rajath Salegame, Suhaas M Bhat, Stanislav Levental, Thomas Dybdahl Ahle, Matthias Jung

Track: long paper (up to 8 pages)

Keywords: Autoformalization, AI Agents, Hardware, Chip Verification, Petri nets, DRAM

TL;DR: We introduce an auto-formalization pipeline and benchmark that translates real-world DRAM specifications into formal artifacts for design verification with AI agents.

Abstract:

The primary goal of Design Verification (DV) is to ensure that a proposed chip design implementation (either in code, or physical form) exactly matches its specification and is free of functional errors in order to avoid costly re-designs. Achieving this often demands extensive manual interpretation, translating the specification document into a formal, testable representation. While AI has made progress in DV, current approaches typically focus on narrow, isolated tasks rather than full end-to-end specification compliance of modern chip designs, failing to capture the complexity of real-world verification.
Our method automatically formalizes natural language memory chip specifications, for industry relevant Dynamic Random Access Memory (DRAM) standards, into a formal representation called \textit{DRAMPyML} that can be used for downstream DV tasks like the generation of SystemVerilog assertions, stimulus, and functional coverage. We also release a benchmarking evaluation harness which can be used to evaluate the evolution of model capabilities (and new approaches) at hardware autoformalization.

Anonymization: This submission has been anonymized for double-blind review via the removal of identifying information such as names, affiliations, and identifying URLs.

Submission Number: 48