An analytical timing-driven placer for modern heterogeneous FPGAs

Zhifeng Lin, Yilu Chen, Yanyue Xie, Chuandong Chen, Jun Yu, Jianli Chen

Abstract: As the feature sizes keep shrinking, interconnect delays have become a major limiting factor for FPGA timing closure. Traditional placement algorithms that address wirelength alone are no longer sufficient to close timing, especially for the large-scale heterogeneous FPGAs. In this paper, we propose an analytical placement algorithm for FPGA timing optimization. By leveraging the look-up table technique, we first present a smoothed routing-architecture-aware timing model to calculate each connection delay rapidly. Then, an effective wirelength and timing co-optimization strategy is developed to produce high-quality placements without timing violations. Finally, a delay optimal region-based detail placement strategy is designed to further improve the timing performance. Compared with Vivado 2023.1 on AMD benchmark suites for xc7k325t device, experimental results show that our algorithm achieves not only a 3.2% improvement in worst slack, but also a 2.5% reduction for routed wirelength.