Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code

Xiankai Meng, Xiang Ji, Guangda Zhang, Jiayu He, Deheng Yang, Fangshu Chen, Jiahui Wang, Chengcheng Yu, Xinlin Zhao, Jiang Wu

Abstract: Hardware description languages are fundamental to modern digital circuit design, allowing engineers to model the structure, behavior, and functionality of complex systems at high levels of abstraction. As formal specifications bridging algorithmic design and physical implementation, HDLs support accurate modeling and efficient hardware development. However, HDL bugs can lead to functional failures, financial losses, and safety risks. Systematically identifying bug patterns in hardware designs provides valuable insights for bug benchmark construction, facilitating bug localization and the development of automated verification tools. Given that high-performance computing systems often rely on custom RTL designs, improving RTL correctness plays an important role in enhancing the efficiency of verification and debugging in HPC hardware development. Despite the growth of open-source hardware initiatives, empirical research in this field still lags behind established practices in software engineering. This paper presents a large-scale empirical study of RTL Verilog bugs, combining automated analysis with statistical pattern discovery. It makes three key contributions: (1) the development of an AST-based automated analysis tool for Verilog code; (2) an examination of over 300 open-source Verilog projects, analyzing more than 15,000 commits and extracting over 1000 bug-fix-related commits; and (3) a comprehensive statistical analysis of bug types and distributions, with a focus on statement-level and expression-level patterns.

External IDs:dblp:journals/tjs/MengJZHYCWYZW25