Irrelevant Data Traffic in Modern Low Power GPU Architectures

Anshujit Sharma, Sushant Kondguli, Michael C. Huang

Abstract: Chip manufacturers are constantly trying to increase the on-chip compute power to meet the ever increasing compute demands of modern computer applications. Such high compute power processor architectures often require a steady supply of large amounts of data to be able to make full use of their raw compute power. Historically, memory technologies have lagged behind the processors in terms of speed. So, memory bandwidth often becomes a performance limiter. Higher memory bandwidth also leads to an increase in the overall energy and power consumption of the system. As a result, reducing off-chip data traffic continues to be an important design problem for future processor architectures. In this paper, we identify a portion of off-chip traffic produced by modern graphics applications that can be avoided while maintaining functional correctness. We note that modern graphics applications produce a lot of intermediate data and that this intermediate data serves no purpose or becomes irrelevant after the application has consumed it. We show that a significant portion of the off-chip traffic is produced by this irrelevant intermediate data. We also propose a mechanism with which this off-chip traffic could be significantly reduced.