A Three Input Look-Up-Table Design Based on Memristor-CMOS

Junwei Sun, Xingtong Zhao, Yanfeng Wang

Abstract: The logic block of field programmable gate array (FPGA) basic unit is mainly composed of look-up-table (LUT). The conventional LUT using the static random access memory (SRAM), which leads to FPGA almost reach the limitation in term of the density, speed, and configuration overhead. In this paper, a new scheme of improved memristor-based look-up-table (MLUT) is proposed. The MLUT circuit, which is compatible with the mainstream circuit in FPGA. The MLUT effectively solving the limitations of field FPGA and MLUT is more efficient in data transmission than traditional LUT. In addition, the proposed circuit can achieve any combination logic function in MLUT by specific configuration. As a case study, a three-input LUT circuit based on memristor is designed and the correctness of the results is simulated in PSPICE software. The MLUT can replace traditional SRAM-based LUTs and further improve FPGA performance.