Supporting Register-based Addressing Modes for in-DRAM PIM ISAs

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Seok Young Kim, Byung Ho Choi, Seokwon Kang, Yongjun Park, Seon Wook Kim

Published: 2025, Last Modified: 29 Dec 2025DAC 2025EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: Processing-in-Memory architecture presents a promising solution to alleviate the data movement bottleneck that arises from transferring data between memory and compute units in traditional processor-centric systems, particularly for DNN applications. However, this architecture introduces two inherent overheads: PIM code offloading and data transferring between CPU and memory. To address these issues, we propose two register-based addressing modes, indexed and base-offset addressing, for DMA descriptor-based in-DRAM PIM ISAs. Our full-system performance evaluation demonstrates that the approach significantly reduces the overheads, resulting in up to 1.94x speedup compared to the baseline PIM, additionally only with $4.65 \%$ area and $8.61 \%$ power consumption.