Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads

James Petrie

Keywords: Verifiable Computing, Hardware Security, HBM, Chiplet, AI Governance

TL;DR: We propose an open-source "Guarantee Chiplet" integrated beneath High Bandwidth Memory stacks in AI accelerators to provide hardware-level attestations for verifiable AI workloads.

Abstract: Potential risks from large-scale AI experiments motivate the development of hardware-level guarantees for computational workloads. We propose Guaranteeable Memory, a novel approach centered around an open-source “guarantee chiplet” integrated beneath High Bandwidth Memory (HBM) stacks within AI accelerators. This chiplet directly observes memory traffic, enabling attestations about executed workloads, including memory snapshots, GPU instructions, or probabilistic checks of the correctness of claimed workloads by verifying random subsets of computations and data transfers. Key advantages of this HBM-based design include direct access to system memory, compatibility with multiple leading accelerators via the HBM standard, and inherent physical tamper-resistance due to its integration geometry. This approach aims to provide trustworthy workload guarantees without relying on the integrity of other system components, including the main accelerator die.

Submission Number: 25