Fast, Robust, and Transferable Prediction for Hardware Logic Synthesis

Ceyu Xu, Pragya Sharma, Tianshu Wang, Lisa Wu Wills

Abstract:

The increasing complexity of computer chips and the slow logic
synthesis process have become major bottlenecks in the hardware
design process, also hindering the ability of hardware generators
to make informed design decisions while considering hardware
costs. While various models have been proposed to predict physical
characteristics of hardware designs, they often suffer from limited
domain adaptability and open-source hardware design data scarcity.
In this paper, we present SNS v2, a fast, robust, and transfer-
able hardware synthesis predictor based on deep learning models.
Inspired by modern natural language processing models, SNS v2
adopts a three-phase training approach encompassing pre-training,
fine-tuning, and domain adaptation, enabling it to leverage more
abundant unlabeled and off-domain training data. Additionally,
we propose a novel contrastive learning approach based on cir-
cuit equivalence to enhance model robustness. Our experiments
demonstrate that SNS v2 achieves two to three orders of magnitude
faster speed compared to conventional EDA tools, while maintain-
ing state-of-the-art prediction accuracy. We also show that SNS v2
can be seamlessly integrated into hardware generator frameworks
for real-time cost estimation, resulting in higher quality design
recommendations in a significantly reduced time frame.