Pushing the Limits of Parallel Discrete Event Simulation for SystemC

Rainer Dömer, Zhongqi Cheng, Daniel Mendoza, Emad Malekzadeh Arasteh

Abstract: The IEEE SystemC language is widely used in industry and academia to model and simulate system-level designs. Despite the availability of multi- and many-core host processors, however, the Accellera reference simulator is still based on sequential discrete event simulation, utilizing only a single core at any time. While many advanced parallel simulation approaches have been proposed, most require modification of the SystemC source code so that the model is free from parallel access conflicts and rely on the designer to manually perform this difficult transformation. The Recoding Infrastructure for SystemC (RISC) project addresses the parallel SystemC simulation problem with automatic compiler-based analysis and source code transformation. A dedicated SystemC compiler and corresponding parallel simulator provide safe static analysis and recoding, and thus automatically achieve fast parallel simulation of SystemC models. We share the RISC framework as open source in order to enable easy evaluation, foster collaboration, and further extend our proof-of-concept implementation.