A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS

Paul N. Whatmough, Shidhartha Das, David M. Bull

Abstract: A 1-GHz Razor FIR accelerator is implemented in a 65-nm CMOS process. Timing-error detection is implemented using Razor latches on critical paths. Real-time DSP systems necessitate fixed-latency error-correction, which is achieved using a combination of two distinct mechanisms. First, marginal timing violations are corrected using a time-borrow tracking algorithm that uses timing-error detection information to track excessive time borrowing. Second, persistent unresolved time borrowing is corrected at the end of the pipeline using a low-overhead approximate error-correction stage which is based on interpolation. Measurements at peak throughput of over 1 GS/s demonstrate an energy-efficiency improvement of 37%, while maintaining 10% supply voltage margin.