SpikeNC: An Accurate and Scalable Simulator for Spiking Neural Network on Multi-Core Neuromorphic Hardware

Lisheng Xie, Jianwei Xue, Liangshun Wu, Faquan Chen, Qingyang Tian, Yifan Zhou, Rendong Ying, Peilin Liu

Abstract: Multi-core neuromorphic hardware for spiking neural networks (SNNs) has garnered considerable attention due to its biological plausibility and energy efficiency. However, the performance of SNN applications on such hardware is constrained by the rigid architecture and interconnection among neuron cores. To enable early-stage evaluation of SNN performance on multi-core neuromorphic hardware, we introduce an accurate and scalable simulator, SpikeNC. We present the entire workflow, ranging from SNN model training to simulation, providing comprehensive insights into both model and Network-on-Chip (NoC) related statistics. Moreover, we identify a considerable amount of time wastage in the widely adopted tick-based synchronous scheme. A three-stage agent-based asynchronous scheme is proposed for fast simulation. We evaluate the performance of deep spiking neural networks (DSNNs) with various scales trained on spike-converted datasets using SpikeNC. The results demonstrate that SpikeNC achieves precise and scalable simulation for SNNs on multi-core neuromorphic hardware. Additionally, the proposed asynchronous scheme significantly reduces the simulation cycles and absolute simulation time by approximately 63 % and 56 % respectively, compared to the synchronous scheme. We also delve into the trade-offs between different design parameters and explore the influence of mapping schemes utilizing SpikeNC.