A 180 Kbit Embeddable MRAM Memory Module

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Joseph J. Nahas, Thomas W. Andre, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino

Published: 01 Jan 2007, Last Modified: 11 Feb 2025CICC 2007EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: 180 Kbit magnetoresistive random access memory (MRAM) designed for embedding in a 0.28 micron CMOS process has been developed. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell. The architecture, write driver, and sense amplifier are described. The use of a test register to characterize and optimize the memory design is also discussed.