Machine-learning based congestion estimation for modern FPGAs

Dani Maarouf, Abeer Alhyari, Ziad Abuowaimer, Timothy Martin, Andrew David Gunter, Gary Grewal, Shawki Areibi, Anthony Vannelli

Abstract:

Avoiding congestion for routing resources has
become one of the most important placement objectives. In
this paper, we present a machine-learning model for accurately and efficiently estimating congestion during FPGA
placement. Compared with the state-of-the-art machinelearning congestion-estimation model, our results show
a 25% improvement in prediction accuracy. This makes
our model competitive with congestion estimates produced
using a global router. However, our model runs, on average,
291x faster than the global router.